~ruther/verilog-riscv-semestral-project

df876b38 — Rutherther 2 years ago
chore: extend memory
7d544e62 — Rutherther 2 years ago
chore: pass in full trace file instead of program name
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
38e84297 — Rutherther 2 years ago
fix: shift left only by 5 bits
740085c8 — Rutherther 2 years ago
fix: lui, force rs1 zero, always add
18eeb2c5 — Rutherther 2 years ago
tests: compile only once, copy proram, memory files to correct locations
1d7c9233 — Rutherther 2 years ago
chore: add python cache to gitignore
51842d38 — Rutherther 2 years ago
feat: add support for official tests
7f5ffd17 — Rutherther 2 years ago
chore: add python to flake
34b74f06 — Rutherther 2 years ago
tests: add python test environment for custom tests
bde9255c — Rutherther 2 years ago
chore: load gcd parameters from memory
37437a00 — Rutherther 2 years ago
chore: remove first unused register
732301c9 — Rutherther 2 years ago
chore: move inital sp to 1020
32388b78 — Rutherther 2 years ago
feat: add support for loading and saving ram from disk
ee0204c8 — Rutherther 2 years ago
feat: pass program to execute by parameter
11422de0 — Rutherther 2 years ago
feat: store c results in memory addr 0
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
5fe03098 — Rutherther 2 years ago
chore: trace memory array
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
e7b5d989 — Rutherther 2 years ago
test: add cpu testbenches for c programs
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