~ruther/verilog-riscv-semestral-project

fix: lui, force rs1 zero, always add
tests: compile only once, copy proram, memory files to correct locations
chore: add python cache to gitignore
feat: add support for official tests
chore: add python to flake
tests: add python test environment for custom tests
chore: load gcd parameters from memory
chore: remove first unused register
chore: move inital sp to 1020
feat: add support for loading and saving ram from disk
feat: pass program to execute by parameter
11422de0 — Rutherther 2 years ago
feat: store c results in memory addr 0
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
5fe03098 — Rutherther 2 years ago
chore: trace memory array
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
e7b5d989 — Rutherther 2 years ago
test: add cpu testbenches for c programs
bb32d2dd — Rutherther 2 years ago
feat: add gcd program for testing
9f4ac4dc — Rutherther 2 years ago
fix: jump according to zero flag, not LSB zero!!
adfdc041 — Rutherther 2 years ago
feat: add branches.c test
0a9a14b7 — Rutherther 2 years ago
test: add ram test
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