~ruther/verilog-riscv-semestral-project

ref: feat/misaligned-reads verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1.0 KiB
38e84297 — Rutherther 2 years ago
fix: shift left only by 5 bits
66fd5da9 — Rutherther 2 years ago
fix: shift by 5 bits in alu
f73ce77d — Rutherther 2 years ago
fix: alu arithmetical shift

Has to have signed as arguments
f8bf441e — Rutherther 2 years ago
chore: move default case
51a684d9 — Rutherther 2 years ago
chore: formatting
8adc02d7 — Rutherther 2 years ago
feat: add basic ram, alu, and register file