~ruther/verilog-riscv-semestral-project

ref: d4e70aa69c3671bba9e02d198267f09cfc493a11 verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1.0 KiB 
fix: shift left only by 5 bits

fix: shift by 5 bits in alu

fix: alu arithmetical shift

Has to have signed as arguments

chore: move default case

chore: formatting

feat: add basic ram, alu, and register file
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