~ruther/verilog-riscv-semestral-project

ref: af6386a7cb0eb3b58cd754956dca300d416cbcde verilog-riscv-semestral-project/src d--------- 
feat: add program counter

feat: add program memory

fix: alu arithmetical shift

Has to have signed as arguments

feat(decoder): implement memory mask, conditional jumps

refactor: parametrize register file

chore: move default case

fix: make rd1, rd2 in register_file regs

feat: add instruction decoder

chore: formatting

feat: add basic ram, alu, and register file
Do not follow this link