~ruther/verilog-riscv-semestral-project

ref: a079c57bf9f1ab9cca6147599107bdd01e034121 verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1.0 KiB 
fix: shift left only by 5 bits

fix: shift by 5 bits in alu

fix: alu arithmetical shift

Has to have signed as arguments

chore: move default case

chore: formatting

feat: add basic ram, alu, and register file