~ruther/verilog-riscv-semestral-project

ref: 2929a779a9d6e451c15f91ac7124f4081e2a04b4 verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1.0 KiB
f73ce77d — Rutherther 2 years ago 
fix: alu arithmetical shift

Has to have signed as arguments
f8bf441e — Rutherther 2 years ago 
chore: move default case
51a684d9 — Rutherther 2 years ago 
chore: formatting
8adc02d7 — Rutherther 2 years ago 
feat: add basic ram, alu, and register file