~ruther/verilog-riscv-semestral-project

ref: f73ce77d4cbe9181f58b2e1c68b6525b9b67dd68 verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1.0 KiB 
fix: alu arithmetical shift

Has to have signed as arguments

chore: move default case

chore: formatting

feat: add basic ram, alu, and register file