feat: implement spi model narrow sck check

fix: divisors list had excess element

fix: selected_divisor range

fix: assumptions about synthesizable code

feat: add initial test for spi peripheral

fix: master didn't go to invalid data when data are read on first cycle of ready

fix: masterslave component inputs tx_valid, rx_ready were outs

feat: implement spi memory mapped peripheral

feat: add test for lsbfirst

feat: add lsbfirst support

chore: remove todo comments

fix: rx, tx disabling

feat: add csn pulse test and rx, tx disabling test

feat: add tests for rx blocking

fix: prevent pulses on tx_ready_o, rx_block assertion when rx is ready

chore: move spi models to separate file

fix: clkgen for various phases and polarities

feat: add tests for clock phase, polarity

fix: support other divisors than 2

fix: multiple issues in design

- setting lost rx data at correct time
- clearing lost rx data on start so the value is determined
- resolving pulses on stuff that depended on zero signal in ctrl
- allowing next tx right after one ended (crucial for divisor = 2)