3 files changed, 28 insertions(+), 21 deletions(-)

M hdl_spi/src/shift_register.vhd
M hdl_spi/src/spi_master.vhd
M hdl_spi/src/spi_masterslave.vhd

@@ 7,14 7,15 @@ entity shift_register is
     SIZE : natural);
 
   port (
-    clk_i   : in  std_logic;
-    rst_in  : in  std_logic;
-    shift_i : in  std_logic;
-    sd_i    : in  std_logic;
-    sd_o    : out std_logic;
-    latch_i : in  std_logic;
-    data_i  : in  std_logic_vector(SIZE - 1 downto 0);
-    data_o  : out std_logic_vector(SIZE - 1 downto 0));
+    clk_i      : in  std_logic;
+    rst_in     : in  std_logic;
+    lsbfirst_i : in  std_logic;
+    shift_i    : in  std_logic;
+    sd_i       : in  std_logic;
+    sd_o       : out std_logic;
+    latch_i    : in  std_logic;
+    data_i     : in  std_logic_vector(SIZE - 1 downto 0);
+    data_o     : out std_logic_vector(SIZE - 1 downto 0));
 
 end entity shift_register;
 


@@ 35,7 36,8 @@ begin  -- architecture a1
   end process set_data;
 
   next_register <= data_i when latch_i = '1' else
-                   curr_register(SIZE - 2 downto 0) & sd_i when shift_i = '1' else
+                   curr_register(SIZE - 2 downto 0) & sd_i when shift_i = '1' and lsbfirst_i = '0' else
+                   sd_i & curr_register(SIZE - 1 downto 1) when shift_i = '1' else
                    curr_register;
 
   sd_o <= curr_register(SIZE - 1);

@@ 141,6 141,7 @@ begin  -- architecture a1
       -- Control
       shift_i => latch_sample_data,     -- sampling
       latch_i => latch_new_tx_data,     -- latching tx data
+      lsbfirst_i => '0',
       -- Parallel
       data_i => tx_data_i,
       data_o => rx_data_o,

@@ 31,6 31,7 @@ entity spi_masterslave is
     div_sel_i            : in    std_logic_vector(DIVISORS_LOG2 - 1 downto 0);
     pulse_csn_i          : in    std_logic;
     rx_block_on_full_i   : in    std_logic;
+    lsbfirst_i           : in    std_logic;
     -- Data
     -- Rx
     rx_en_i              : in    std_logic;


@@ 63,6 64,7 @@ architecture a1 of spi_masterslave is
   signal latch_new_tx_data     : std_logic;
 
   signal tx_input_data : std_logic;
+  signal tx_input_index : natural range 0 to MAX_SIZE - 1;
   signal tx_serial_data : std_logic_vector(0 downto 0);
   signal rx_serial_data : std_logic;
 


@@ 208,25 210,27 @@ begin  -- architecture a1
       sample_data_o    => slave_latch_sample_data,
       change_data_o    => slave_latch_change_data);
 
-  shift_register: entity work.shift_register
+  shift_register : entity work.shift_register
     generic map (
       SIZE => MAX_SIZE)
     port map (
-      clk_i => clk_i,
-      rst_in => rst_n,
+      clk_i      => clk_i,
+      rst_in     => rst_n,
       -- Control
-      shift_i => latch_sample_data,     -- sampling
-      latch_i => latch_new_tx_data,     -- latching tx data
+      shift_i    => latch_sample_data,  -- sampling
+      latch_i    => latch_new_tx_data,  -- latching tx data
+      lsbfirst_i => lsbfirst_i,
       -- Parallel
-      data_i => tx_data_i,
-      data_o => rx_data_o,
+      data_i     => tx_data_i,
+      data_o     => rx_data_o,
       -- Serial
-      sd_i => rx_serial_data,
-      sd_o => open);
+      sd_i       => rx_serial_data,
+      sd_o       => open);
 
-  tx_input_data <= tx_data_i(selected_size - 1) when latch_new_tx_data = '1' and latch_change_data_out = '1' else
-                   rx_data_o(selected_size - 1) when selected_size > 0 else
-                   'X';
+  tx_input_index <= 0 when selected_size = 0 else
+                    selected_size - 1 when lsbfirst_i = '0' else 0;
+  tx_input_data <= tx_data_i(tx_input_index) when latch_new_tx_data = '1' and latch_change_data_out = '1' else
+                   rx_data_o(tx_input_index);
 
   mosi_reg : entity work.reg
     generic map (