~ruther/vhdl-spi-2

064c8c0056d9f2aef82ec72cf18d9d6357a13f15 — Rutherther 3 months ago b057342
chore: remove todo comments
1 files changed, 0 insertions(+), 6 deletions(-)

M hdl_spi/tests/test_spi_masterslave.py
M hdl_spi/tests/test_spi_masterslave.py => hdl_spi/tests/test_spi_masterslave.py +0 -6
@@ 505,12 505,6 @@ async def csn_pulse(dut):

    await Timer(100, "ns")

# Rx blocking - Can't go to another transmission until data confirmed.
  # When data read a bit later, and csn pulsing is enabled, the csn should still pulse, before data are obtained

# rx_en off - miso should be ignored, no rx_valid is always 0. Tx works fine
# tx_en off - mosi should be Z, tx_ready is always 0. Rx works fine

def spi_tests_runner():
    hdl_toplevel_lang = "vhdl"
    sim = os.getenv("SIM", "questa")

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