fix: masterslave component inputs tx_valid, rx_ready were outs
1 files changed, 2 insertions(+), 2 deletions(-) M hdl_spi/src/spi_masterslave.vhd
M hdl_spi/src/spi_masterslave.vhd => hdl_spi/src/spi_masterslave.vhd +2 -2
@@ 37,11 37,11 @@ entity spi_masterslave is rx_en_i : in std_logic; rx_data_o : out std_logic_vector(get_max_natural(SIZES) - 1 downto 0); rx_valid_o : out std_logic; rx_ready_i : out std_logic; rx_ready_i : in std_logic; -- Tx tx_en_i : in std_logic; tx_data_i : in std_logic_vector(get_max_natural(SIZES) - 1 downto 0); tx_valid_i : out std_logic; tx_valid_i : in std_logic; tx_ready_o : out std_logic; -- State busy_o : out std_logic;