1 files changed, 1 insertions(+), 1 deletions(-)

M hdl_spi/src/spi_clkgen.vhd

@@ 32,7 32,7 @@ architecture a1 of spi_clkgen is
   signal curr_running : std_logic;
   signal next_running : std_logic;
 
-  signal selected_divisor : natural range 0 to MAX - 1 := 1;
+  signal selected_divisor : natural range 0 to MAX := 1;
   signal changing : std_logic;
 
   signal curr_counter : integer range 0 to MAX - 1;