1 files changed, 2 insertions(+), 1 deletions(-)

M hdl_spi/src/spi_master_ctrl.vhd

@@ 243,7 243,7 @@ begin  -- architecture a1
 
     if tx_en_i = '0' then
       next_tx_state <= IDLE;
-      tx_got_data <= not rx_block;               -- simulate always receiving new data
+      tx_got_data <= not rx_block and tx_valid_i;               -- simulate always receiving new data
     end if;
   end process tx_state;
 


@@ 258,6 258,7 @@ begin  -- architecture a1
     case curr_rx_state is
       when IDLE =>
         next_rx_state <= RX_INVALID_DATA;
+        rx_block <= '0';
       when RX_GOT_DATA =>
         rx_valid_o <= '1';
         if rx_ready_i = '1' or tx_got_data = '1' then