1 files changed, 10 insertions(+), 3 deletions(-)

M hdl_spi/src/spi_master_ctrl.vhd

@@ 219,8 219,13 @@ begin  -- architecture a1
           next_tx_state <= TX_WAITING;
         end if;
       when TX_WAITING =>
-        if transmission_done = '1' and rx_block = '0' then
-          tx_ready_o <= '1';
+        if (transmission_done = '1' or curr_state /= SHIFTING) and rx_block = '0' then
+
+          -- prevent pulse...
+          if rx_ready_i = '1' or rx_block_on_full_i = '0' then
+            tx_ready_o <= '1';
+          end if;
+
           next_tx_state <= TX_LATCHING_DATA;
 
           if tx_valid_i = '1' then


@@ 267,7 272,9 @@ begin  -- architecture a1
       when RX_INVALID_DATA =>
         rx_block <= '0';
         if transmission_done = '1' then
-          rx_block <= rx_block_on_full_i;
+          if rx_ready_i = '0' then
+            rx_block <= rx_block_on_full_i;
+          end if;
           next_rx_state <= RX_GOT_DATA;
           rx_valid_o <= '1';            -- TODO check
         end if;