fix: clock polarity on csn falling and rising. Proper wait after csn falling and before csn rising

fix: make ios tri state when disabled

fix: csn was rising too soon for divisors > 2

fix: short last sck pulse on slower clock

fix: divisors list had excess element

fix: selected_divisor range

fix: assumptions about synthesizable code

fix: master didn't go to invalid data when data are read on first cycle of ready

fix: masterslave component inputs tx_valid, rx_ready were outs

feat: implement spi memory mapped peripheral

feat: add lsbfirst support

fix: rx, tx disabling

fix: prevent pulses on tx_ready_o, rx_block assertion when rx is ready

fix: clkgen for various phases and polarities

fix: support other divisors than 2

fix: multiple issues in design

- setting lost rx data at correct time
- clearing lost rx data on start so the value is determined
- resolving pulses on stuff that depended on zero signal in ctrl
- allowing next tx right after one ended (crucial for divisor = 2)

fix: sck generation

Sampling and changing was offset by one clock,
which is unnecesary. The clock wasn't correct
frequency, ie. divisor 2 led to division by 3

fix: master_ctrl_rst_n shou be used, not master_ctrl_rst, start_clock is split

fix: do not pass rx_serial_o from spi_multiplexor when not enabled

fix: prevent slave ctrl sending X's