1 files changed, 4 insertions(+), 7 deletions(-)

M hdl_spi/src/spi_masterslave.vhd

@@ 66,8 66,6 @@ architecture a1 of spi_masterslave is
   signal tx_serial_data : std_logic_vector(0 downto 0);
   signal rx_serial_data : std_logic;
 
-  signal start_clock : std_logic;
-
   signal selected_size : natural;
 
   signal master_en : std_logic;


@@ 95,7 93,6 @@ architecture a1 of spi_masterslave is
   signal master_tx_ready : std_logic;
   signal master_busy : std_logic;
   signal master_err_lost_rx_data : std_logic;
-  signal master_ctrl_rst : std_logic;
   signal master_csn : std_logic;
   signal master_csn_en : std_logic;
   signal master_mosi_en : std_logic;


@@ 137,7 134,7 @@ begin  -- architecture a1
       tx_ready_o           => master_tx_ready,
       busy_o               => master_busy,
       err_lost_rx_data_o   => master_err_lost_rx_data,
-      rst_on               => master_ctrl_rst,
+      rst_on               => master_ctrl_rst_n,
       csn_o                => master_csn,
       csn_en_o             => master_csn_en,
       mosi_en_o            => master_mosi_en,


@@ 186,7 183,7 @@ begin  -- architecture a1
     port map (
       clk_i            => clk_i,
       rst_in           => master_ctrl_rst_n,
-      start_i          => start_clock,
+      start_i          => master_start_clock,
       div_sel_i        => div_sel_i,
       clock_polarity_i => clock_polarity_i,
       clock_phase_i    => clock_phase_i,


@@ 224,7 221,7 @@ begin  -- architecture a1
       sd_i => rx_serial_data,
       sd_o => open);
 
-  tx_input_data <= rx_data_o(selected_size - 1);
+  tx_input_data <= rx_data_o(selected_size - 1) when selected_size > 0 else 'X';
 
   mosi_reg : entity work.reg
     generic map (


@@ 260,7 257,7 @@ begin  -- architecture a1
       busy_o              => busy_o,
       err_lost_rx_data_i  => master_err_lost_rx_data,
       err_lost_rx_data_o  => err_lost_rx_data_o,
-      rst_in              => master_ctrl_rst,
+      rst_in              => master_ctrl_rst_n,
       rst_on              => ctrl_rst_n,
       latch_tx_data_i     => master_latch_new_tx_data,
       latch_tx_data_o     => latch_new_tx_data,