~ruther/verilog-riscv-semestral-project

verilog-riscv-semestral-project/src/control_unit.sv -rw-r--r-- 3.3 KiB
79c7be5c — Rutherther 2 years ago main
chore: remove unnecessary executable flags

Closes #4.
f8e4e3ed — Rutherther 2 years ago
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
89310129 — Rutherther 2 years ago
feat: implement pipeline
740085c8 — Rutherther 2 years ago
fix: lui, force rs1 zero, always add
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
bc02aba5 — Rutherther 2 years ago
fix: make sure alu is zeroed on memory load, write, jump
02405eec — Rutherther 2 years ago
fix: force alu operation to addition for storing memory and pc
e44bfc9e — Rutherther 2 years ago
fix: propagate conditional jump from control_unit
52b05e5d — Rutherther 2 years ago
feat: add control_unit wrapper over instruction_decoder