~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/src/control_unit.sv -rw-r--r-- 3.3 KiB
chore: remove unnecessary executable flags

Closes #4.
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
feat: implement pipeline
fix: lui, force rs1 zero, always add
feat: implement ebreak

Breaks the processor, can
exit the testcase
feat: implement sb, sh, lb, lh support via masking
fix: make sure alu is zeroed on memory load, write, jump
fix: force alu operation to addition for storing memory and pc
fix: propagate conditional jump from control_unit
feat: add control_unit wrapper over instruction_decoder
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