~ruther/verilog-riscv-semestral-project

ref: bb32d2ddcd68d2cf131760d9c1d99f9107c912f8 verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1.0 KiB 
fix: shift by 5 bits in alu

fix: alu arithmetical shift

Has to have signed as arguments

chore: move default case

chore: formatting

feat: add basic ram, alu, and register file