~ruther/verilog-riscv-semestral-project

ref: 7581533cf757a3434d732348b90205ff6be3b404 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 2.6 KiB
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
feat: implement pipeline
fix: linker file issues, naming of linked file
chore: pass PROGRAM argument to objdump make target
fix: make Makefile work with memory load, write files
chore: pass in full trace file instead of program name
feat: add support for official tests
feat: pass program to execute by parameter
chore: trace memory array
fix(Makefile): make objdump and all testbenches work
chore: add makefile for both verilog and c
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