~ruther/verilog-riscv-semestral-project

ref: 73cf8a16605792f3455e04745c5e0007e1f08be5 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 2.2 KiB 
chore: pass in full trace file instead of program name

feat: add support for official tests

feat: pass program to execute by parameter

chore: trace memory array

fix(Makefile): make objdump and all testbenches work

chore: add makefile for both verilog and c