~ruther/verilog-riscv-semestral-project

ref: 7d544e62c57a7e944d1572d147f7b271333a75aa verilog-riscv-semestral-project/Makefile -rwxr-xr-x 2.2 KiB
chore: pass in full trace file instead of program name
feat: add support for official tests
feat: pass program to execute by parameter
chore: trace memory array
fix(Makefile): make objdump and all testbenches work
chore: add makefile for both verilog and c
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