~ruther/verilog-riscv-semestral-project

ref: 64d33d2582c219e00b6c1f7573501ee713da0967 verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1.0 KiB
fix: alu arithmetical shift

Has to have signed as arguments
chore: move default case
chore: formatting
feat: add basic ram, alu, and register file