~ruther/verilog-riscv-semestral-project

ref: 64d33d2582c219e00b6c1f7573501ee713da0967 verilog-riscv-semestral-project/src d---------
feat: add program memory
fix: alu arithmetical shift

Has to have signed as arguments
feat(decoder): implement memory mask, conditional jumps
refactor: parametrize register file
chore: move default case
fix: make rd1, rd2 in register_file regs
feat: add instruction decoder
chore: formatting
feat: add basic ram, alu, and register file
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