~ruther/verilog-riscv-semestral-project

ref: 52b05e5db08bd4360a157609d8529e01ad35cfd9 verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1.0 KiB 
fix: alu arithmetical shift

Has to have signed as arguments

chore: move default case

chore: formatting

feat: add basic ram, alu, and register file