~ruther/verilog-riscv-semestral-project

ref: 300c2dd744c0a39f8ca60ce97c3015c7af4c27cf verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1.0 KiB 
fix: alu arithmetical shift

Has to have signed as arguments

chore: move default case

chore: formatting

feat: add basic ram, alu, and register file