~ruther/verilog-riscv-semestral-project

ref: 27fcb8d9421b49a1d1545cb4fb80f9c6f03ebaf8 verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1.0 KiB 
fix: alu arithmetical shift

Has to have signed as arguments

chore: move default case

chore: formatting

feat: add basic ram, alu, and register file