~ruther/verilog-riscv-semestral-project

ref: d4e70aa69c3671bba9e02d198267f09cfc493a11 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 2.5 KiB
d4e70aa6 — Rutherther 2 years ago
fix: linker file issues, naming of linked file
94c41794 — Rutherther 2 years ago
chore: pass PROGRAM argument to objdump make target
280332ea — Rutherther 2 years ago
fix: make Makefile work with memory load, write files
7d544e62 — Rutherther 2 years ago
chore: pass in full trace file instead of program name
51842d38 — Rutherther 2 years ago
feat: add support for official tests
ee0204c8 — Rutherther 2 years ago
feat: pass program to execute by parameter
5fe03098 — Rutherther 2 years ago
chore: trace memory array
cc87c7b8 — Rutherther 2 years ago
fix(Makefile): make objdump and all testbenches work
707b5bfc — Rutherther 2 years ago
chore: add makefile for both verilog and c