~ruther/verilog-riscv-semestral-project

ref: d4e70aa69c3671bba9e02d198267f09cfc493a11 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 2.5 KiB
fix: linker file issues, naming of linked file
chore: pass PROGRAM argument to objdump make target
fix: make Makefile work with memory load, write files
chore: pass in full trace file instead of program name
feat: add support for official tests
feat: pass program to execute by parameter
chore: trace memory array
fix(Makefile): make objdump and all testbenches work
chore: add makefile for both verilog and c
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