~ruther/verilog-riscv-semestral-project

ref: c682cc068ee41da1b00fbd51dfb79f9cd5560d0d verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 7.0 KiB
feat: implement ebreak

Breaks the processor, can
exit the testcase
fix: jump according to zero flag, not LSB zero!!
feat: implement sb, sh, lb, lh support via masking
fix: do not set subtract for non-R instructions
fix: make immediates sign extended
fix: do not use immediate in alu src for SB
feat(decoder): implement memory mask, conditional jumps
feat: add instruction decoder
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