~ruther/verilog-riscv-semestral-project

ref: 9f4ac4dc09c9ccb93c6b1d9726bc7543ff09de00 verilog-riscv-semestral-project/src d---------
32ebeea6 — Rutherther 2 years ago
feat(decoder): implement memory mask, conditional jumps
24eccbe0 — Rutherther 2 years ago
refactor: parametrize register file
f8bf441e — Rutherther 2 years ago
chore: move default case
69ced879 — Rutherther 2 years ago
fix: make rd1, rd2 in register_file regs
e3c95ad3 — Rutherther 2 years ago
feat: add instruction decoder
51a684d9 — Rutherther 2 years ago
chore: formatting
8adc02d7 — Rutherther 2 years ago
feat: add basic ram, alu, and register file