~ruther/verilog-riscv-semestral-project (9f4ac4dc09c9ccb93c6b1d9726bc7543ff09de00): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

9f4ac4dc — Rutherther fix: jump according to zero flag, not LSB zero!! 1 year, 5 months ago

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.envrc

10 bytes

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.gitignore

90 bytes

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Makefile

1.4 KiB

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flake.lock

1.5 KiB

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flake.nix

1.3 KiB

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programs/

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src/

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testbench/

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