~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/src/instruction_decoder.sv -rw-r--r-- 7.1 KiB
chore: remove unnecessary executable flags

Closes #4.
fix: use reg for procedural assignments
fix: lui, force rs1 zero, always add
feat: implement ebreak

Breaks the processor, can
exit the testcase
fix: jump according to zero flag, not LSB zero!!
feat: implement sb, sh, lb, lh support via masking
fix: do not set subtract for non-R instructions
fix: make immediates sign extended
fix: do not use immediate in alu src for SB
feat(decoder): implement memory mask, conditional jumps
feat: add instruction decoder
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