~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/programs d---------
chore: remove unnecessary executable flags

Closes #4.
fb02ebb2 — Rutherther 2 years ago
Merge pull request #2 from Rutherther/feat/misaligned-reads

Support misaligned read
e5d2c0c5 — Rutherther 2 years ago
tests: add simple ma.c program for testing misaligned access
d4e70aa6 — Rutherther 2 years ago
fix: linker file issues, naming of linked file
a079c57b — Rutherther 2 years ago
tests: add more custom tests
bde9255c — Rutherther 2 years ago
chore: load gcd parameters from memory
732301c9 — Rutherther 2 years ago
chore: move inital sp to 1020
11422de0 — Rutherther 2 years ago
feat: store c results in memory addr 0
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
bb32d2dd — Rutherther 2 years ago
feat: add gcd program for testing
adfdc041 — Rutherther 2 years ago
feat: add branches.c test
6ce1c838 — Rutherther 2 years ago
chore: remove gcc generated file
30a7f949 — Rutherther 2 years ago
feat: add basic testing programs