~ruther/verilog-riscv-semestral-project

e5d2c0c5de0541507c602b1d9a5cff2a0cc88494 — Rutherther 1 year, 3 months ago b89bec4
tests: add simple ma.c program for testing misaligned access
1 files changed, 14 insertions(+), 0 deletions(-)

A programs/ma.c
A programs/ma.c => programs/ma.c +14 -0
@@ 0,0 1,14 @@
int main() {

    // 0x0F000000
    __asm__(" \
      addi x1, x0, 0x0F\n \
      sll x1, x1, 24\n    \
      addi x1, x1, 0x0A\n \
      sw x1, 1(x0)\n      \
      lw x2, 1(x0)\n      \
      nop\n               \
      nop\n               \
      ebreak\n            \
    ");
}

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