~ruther/verilog-riscv-semestral-project

ref: 6ce1c83859b56b514f0a4536ddb388cacc77773e verilog-riscv-semestral-project/src d---------
24eccbe0 — Rutherther 2 years ago 
refactor: parametrize register file
f8bf441e — Rutherther 2 years ago 
chore: move default case
69ced879 — Rutherther 2 years ago 
fix: make rd1, rd2 in register_file regs
e3c95ad3 — Rutherther 2 years ago 
feat: add instruction decoder
51a684d9 — Rutherther 2 years ago 
chore: formatting
8adc02d7 — Rutherther 2 years ago 
feat: add basic ram, alu, and register file