~ruther/verilog-riscv-semestral-project

ref: 24eccbe0e5c0dabfc068a993b5167510756a4e22 verilog-riscv-semestral-project/src d--------- 
refactor: parametrize register file

chore: move default case

fix: make rd1, rd2 in register_file regs

feat: add instruction decoder

chore: formatting

feat: add basic ram, alu, and register file
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