~ruther/verilog-riscv-semestral-project

ref: 66d141635b81de276634d3d9f97fe46c0ffb2f32 verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 7.1 KiB
c5e322db — Rutherther 2 years ago
fix: use reg for procedural assignments
740085c8 — Rutherther 2 years ago
fix: lui, force rs1 zero, always add
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
9f4ac4dc — Rutherther 2 years ago
fix: jump according to zero flag, not LSB zero!!
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
2867e246 — Rutherther 2 years ago
fix: do not set subtract for non-R instructions
2f09f768 — Rutherther 2 years ago
fix: make immediates sign extended
27fcb8d9 — Rutherther 2 years ago
fix: do not use immediate in alu src for SB
32ebeea6 — Rutherther 2 years ago
feat(decoder): implement memory mask, conditional jumps
e3c95ad3 — Rutherther 2 years ago
feat: add instruction decoder