~ruther/verilog-riscv-semestral-project: src/alu.sv 24eccbe0e5c0dabfc068a993b5167510756a4e22

~ruther/verilog-riscv-semestral-project

ref: 24eccbe0e5c0dabfc068a993b5167510756a4e22 verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1008 bytes

f8bf441e — Rutherther 1 year, 8 months ago

chore: move default case

51a684d9 — Rutherther 1 year, 9 months ago

chore: formatting

8adc02d7 — Rutherther 1 year, 9 months ago

feat: add basic ram, alu, and register file