~ruther/verilog-riscv-semestral-project: src/alu.sv f8bf441ea1e4cf7b0e609b80aecca786fa2a48f3

~ruther/verilog-riscv-semestral-project

ref: f8bf441ea1e4cf7b0e609b80aecca786fa2a48f3 verilog-riscv-semestral-project/src/alu.sv -rwxr-xr-x 1008 bytes

f8bf441e — Rutherther 1 year, 5 months ago

chore: move default case

51a684d9 — Rutherther 1 year, 6 months ago

chore: formatting

8adc02d7 — Rutherther 1 year, 6 months ago

feat: add basic ram, alu, and register file