~ruther/verilog-riscv-semestral-project

ref: 057ee98bbecfb8a284b67bef50b04b70ae18e220 verilog-riscv-semestral-project/src d--------- 
refactor: parametrize register file

chore: move default case

fix: make rd1, rd2 in register_file regs

feat: add instruction decoder

chore: formatting

feat: add basic ram, alu, and register file
Do not follow this link