~ruther/verilog-riscv-semestral-project (057ee98bbecfb8a284b67bef50b04b70ae18e220): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

057ee98b — Rutherther chore: add generated bin, obj gitignore files 1 year, 7 months ago

-rwxr-xr-x

.envrc

10 bytes

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.gitignore

90 bytes

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Makefile

1.4 KiB

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flake.lock

1.5 KiB

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flake.nix

1.3 KiB

d---------

programs/

d---------

src/

d---------

testbench/

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