feat: add vitis and vivado projects

fix(stm): receive 16 bit values with spi

feat(stm): Echo received number back

fix(stm_spi_funduino): reception of spi numbers

fix: clock polarity on csn falling and rising. Proper wait after csn falling and before csn rising

fix: make ios tri state when disabled

tests: add proper checks for clock polarity before and after csn

tests: fix _t meaning (tri state)

fix: csn was rising too soon for divisors > 2

tests: properly account for soonly rising csn

tests: fix peripheral interrupt test - wrong check for rx buffer full

fix: short last sck pulse on slower clock

tests: add spi_peripheral 'application' testcase

tests: add test for interrupts spi_peripheral

feat(stm): implement proper slave initialization

feat: add test for max divisor (256)

feat: implement spi model narrow sck check

fix: divisors list had excess element

fix: selected_divisor range

fix: assumptions about synthesizable code