1 files changed, 15 insertions(+), 1 deletions(-)

M hdl_spi/models/spi_models.py

@@ 158,8 158,12 @@ class SpiSlave:
                 while len > 0:
                     sampling = self.config.sampling(self.sck)
                     shifting = self.config.shifting(self.sck)
+                    csn_rising = RisingEdge(self.csn)
                     timeout = Timer(self.config.sck_period * 2, self.config.sck_period_unit)
-                    res = await First(sampling, shifting, timeout)
+                    res = await First(sampling, shifting, csn_rising, timeout)
+
+                    if res == csn_rising:
+                        raise Exception("CSN rising too soon!")
 
                     if res == timeout:
                         self._log.error("Got no sck edge in time!")


@@ 188,6 192,16 @@ class SpiSlave:
                 if self.config.csn_pulse:
                     break
 
+            sampling = self.config.sampling(self.sck)
+            csn_rising = RisingEdge(self.csn)
+            timeout = Timer(self.config.sck_period * 2, self.config.sck_period_unit)
+            res = await First(shifting, csn_rising, timeout)
+
+            if res == csn_rising:
+                raise Exception("CSN rising too soon!")
+            if res == timeout:
+                raise Exception("No sampling edge nor csn rising!")
+
             # now wait for csn rising
             sim_time = get_sim_time(self.config.sck_period_unit)
             while sim_time == get_sim_time(self.config.sck_period_unit):