3 files changed, 46 insertions(+), 1 deletions(-)

M stm_spi_funduino/include/spi.h
M stm_spi_funduino/src/main.c
M stm_spi_funduino/src/spi.c

@@ 31,6 31,10 @@ void spi_master_configure(spi_t *spi, bool sw_nss, bool clock_polarity,
                           bool clock_phase, spi_frame_orientation_t orientation, spi_frame_format_t format);
 void spi_master_enable(spi_t* spi, bool enable);
 
+void spi_slave_configure(spi_t *spi, bool sw_nss, bool clock_polarity,
+                         bool clock_phase, spi_frame_orientation_t orientation, spi_frame_format_t format);
+void spi_slave_enable(spi_t *spi, bool enable);
+
 uint16_t spi_transmit(spi_t* spi, uint16_t* data, uint16_t size);
 uint16_t spi_receive(spi_t *spi, uint16_t *buffer, uint16_t max_size);
 

@@ 8,6 8,7 @@
 #include "display.h"
 #include "delay.h"
 #include "uart.h"
+#include "spi.h"
 
 void hard_fault_handler() {
   while(1) {}


@@ 71,6 72,7 @@ void SystemCoreClockSetHSI(void) {
 
 display_t display;
 timer_t display_timer;
+spi_t spi;
 uart_t uart;
 
 typedef struct {


@@ 134,6 136,28 @@ void main()
     usart_configure_receiver(&uart, true);
   }
 
+  {
+    pin_t pin_miso;
+    pin_t pin_mosi;
+    pin_t pin_csn;
+    pin_t pin_sck;
+
+    pin_init(&pin_mosi, GPIOA, 7);
+    pin_init(&pin_miso, GPIOA, 6);
+    pin_init(&pin_csn, GPIOA, 4);
+    pin_init(&pin_sck, GPIOB, 3);
+
+    pin_into_alternate(&pin_miso, 5);
+    pin_into_alternate(&pin_mosi, 5);
+    pin_into_alternate(&pin_sck, 5);
+    pin_into_alternate(&pin_csn, 5);
+
+    spi_init(&spi, pin_csn, SPI1, 1);
+    spi_slave_configure(&spi, false, false, false, SPI_MSB_FIRST, SPI_FRAME_8_BIT);
+    spi_enable_interrupt(&spi, false, true);
+    spi_slave_enable(&spi, true);
+  }
+
   timer_init(&display_timer, TIM3, 3);
   timer_configure(&display_timer, 0, 500, 0);
   timer_set_refresh(&display_timer, 4);


@@ 147,10 171,14 @@ void main()
 
   // Application
   while (1) {
-    if (spi_receive(&uart, &buffer[idx], 1) == 0) {
+    uint16_t rx;
+    if (spi_receive(&spi, &rx, 1) == 0) {
       continue;
     }
 
+    buffer[idx] = (char)rx;
+    usart_transmit(&uart, &buffer[idx], 1);
+
     if (buffer[idx] != '\n') {
       idx++;
       continue;

@@ 28,6 28,19 @@ void spi_master_enable(spi_t *spi, bool enable) {
   reg_write_bits(&spi->periph->CR1, enable << SPI_CR1_SPE_Pos, SPI_CR1_SPE);
 }
 
+void spi_slave_configure(spi_t *spi, bool sw_nss, bool clock_polarity,
+                          bool clock_phase, spi_frame_orientation_t orientation, spi_frame_format_t format) {
+  reg_write_bits(&spi->periph->CR1,
+                 (sw_nss << SPI_CR1_SSM_Pos) | (format << SPI_CR1_DFF_Pos) |
+                     (orientation << SPI_CR1_LSBFIRST_Pos) |
+                     (0 << SPI_CR1_BIDIMODE_Pos) | (0 << SPI_CR1_MSTR_Pos) |
+                 (clock_polarity << SPI_CR1_CPOL_Pos) | (clock_phase << SPI_CR1_CPHA_Pos),
+                 SPI_CR1_SSM_Msk | SPI_CR1_DFF_Msk | SPI_CR1_LSBFIRST_Msk | SPI_CR1_BIDIMODE_Msk | SPI_CR1_MSTR_Msk | SPI_CR1_CPOL_Msk | SPI_CR1_CPHA_Msk);
+}
+void spi_slave_enable(spi_t *spi, bool enable) {
+  reg_write_bits(&spi->periph->CR1, enable << SPI_CR1_SPE_Pos, SPI_CR1_SPE);
+}
+
 uint16_t spi_transmit(spi_t *spi, uint16_t *data, uint16_t size) {
   pin_reset(&spi->csn);
   for (int16_t i = 0; i < size; i++) {