~ruther/verilog-riscv-semestral-project

ref: f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2 verilog-riscv-semestral-project/programs d---------
fix: linker file issues, naming of linked file
tests: add more custom tests
chore: load gcd parameters from memory
chore: move inital sp to 1020
feat: store c results in memory addr 0
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
feat: add gcd program for testing
feat: add branches.c test
chore: remove gcc generated file
feat: add basic testing programs
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