~ruther/verilog-riscv-semestral-project

ref: e7b5d989532b0690f2b0ef3a1b7a0072903c0d51 verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.9 KiB 
fix: jump according to zero flag, not LSB zero!!

feat: implement sb, sh, lb, lh support via masking

fix: do not set subtract for non-R instructions

fix: make immediates sign extended

fix: do not use immediate in alu src for SB

feat(decoder): implement memory mask, conditional jumps

feat: add instruction decoder
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