~ruther/verilog-riscv-semestral-project

ref: c682cc068ee41da1b00fbd51dfb79f9cd5560d0d verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.5 KiB 
chore: trace memory array

fix(Makefile): make objdump and all testbenches work

chore: add makefile for both verilog and c
Do not follow this link