~ruther/verilog-riscv-semestral-project: Makefile 5fe030988a21d47dd13af35a9b8697b2181cb6b7

~ruther/verilog-riscv-semestral-project

ref: 5fe030988a21d47dd13af35a9b8697b2181cb6b7 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.5 KiB

5fe03098 — Rutherther 2 years ago

chore: trace memory array

cc87c7b8 — Rutherther 2 years ago

fix(Makefile): make objdump and all testbenches work

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c