~ruther/verilog-riscv-semestral-project

ref: bde9255cf35820314e882969060f77f5cbd6c460 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 2.2 KiB
ee0204c8 — Rutherther 2 years ago
feat: pass program to execute by parameter
5fe03098 — Rutherther 2 years ago
chore: trace memory array
cc87c7b8 — Rutherther 2 years ago
fix(Makefile): make objdump and all testbenches work
707b5bfc — Rutherther 2 years ago
chore: add makefile for both verilog and c