~ruther/verilog-riscv-semestral-project

ref: bde9255cf35820314e882969060f77f5cbd6c460 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 2.2 KiB 
feat: pass program to execute by parameter

chore: trace memory array

fix(Makefile): make objdump and all testbenches work

chore: add makefile for both verilog and c
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